A cardiac pacemaker is a medical device that can effectively treat cardiac arrhythmias by delivering pulse currents at a certain frequency to stimulate the heart to perform the blood-pumping function. The cardiac pacemaker employs a pulse generator to sense cardiac electrical signals and delivers pacing pulses as needed. For example, after the cardiac pacemaker senses an intrinsic atrial event via electrocardiogram (EGM) signal, the pulse generator sets an atrial sense refractory period and a lower rate limit and generates a pacing pulse at a proper time.
In the early ages, pacing control for cardiac pacemakers was performed by digital circuits incorporating pacing state machines. With the complexity of cardiac pacemaker functions increasing, cardiac pacemaker manufacturers added microprocessor cores to the digital circuits. The microprocessor cores were primarily responsible for data statistics and more sophisticated therapeutic functions while the logic control capabilities for the cardiac pacemaker functions are retained in the digital circuits.
In an existing cardiac pacemaker system, a digital circuit performs a great amount of pacemaker-related logic control, such as determining a variety of pacing modes including DDD, VVI, etc. This makes the performance of the cardiac pacemaker system highly hardware-dependent, which is not conducive to the expansion of functionality. In addition, reliability and verification of the digital circuit requires voluminous human and material resources and the system verification of the performance of the cardiac pacemaker system is thus not an easy task.
In another existing cardiac pacemaker system, pacing timing logics are provided by a microprocessor core and a supporting digital circuit. However, such a cardiac pacemaker system requires a great effort in the design of an application-specific integrated circuit (ASIC).